1. Field of the Invention
The invention relates to computer busing systems, and more particularly to a method of and apparatus for determining the configuration and types of boards installed on a computer bus.
2. Description of the Related Art
The microcomputer industry has experienced tremendous growth over the last twenty years. From the days of its infancy when only a few interested "hackers" could fathom its quirks and nuances, the microcomputer has now evolved into a powerful business and personal tool found on virtually every office desk and in virtually every home.
The microcomputer's road to success has not been without its problems, however. While advances occur at an astounding pace, those advances must accommodate the standards found in the then existing base of microcomputer systems. This is known as upwards compatibility. To maintain such compatibility, the industry has seen one microcomputer standard laid on top of another, with a resulting hodgepodge of standards-within-standards that designers must maintain to allow existing users to upgrade their equipment. These multiple standards gradually shed their oldest layers, replacing them with new layers reflecting the state-of-the-art. In this way, only the very oldest microcomputer systems become obsolete.
One early idea to enhance microcomputer systems was the addition of hardware enhancing boards. These boards were generally plugged into a system bus to provide added functionality, such as telecommunications, disk storage, and improved video. These boards obviously had to conform to some standard. With the introduction of the IBM PC by International Business Machines Corp., and the later introduction of the PC/AT by IBM, the AT system bus soon became a de facto standard known as the Industry Standard Architecture bus, or the ISA bus. The AT bus accommodated both the 8-bit boards of the PC and newer 16-bit boards developed for the AT. Third-party manufacturers could economically design standard boards compatible with the wide variety of IBM PC and AT compatible microcomputer systems.
Further advances in microprocessor technology, however, pushed the ISA bus to its limits. For this reason, another "layer" was added to the ISA bus standard. This added layer became known as the Extended Industry Standard Architecture bus, or the EISA bus. Boards designed for the EISA bus had more pins, providing a wider data path for information to flow through the microcomputer system bus, analogous to adding lanes to a highway. The EISA bus also added more address lines to the standard, permitting more memory locations to be individually specified, much as would adding more digits to a phone number or a zip code.
One limitation of the ISA bus involved its method of handling I/O addressing. An address enable signal (AEN) was driven low by an ISA bus master to indicate to all of the cards that the currently asserted address was an I/O address or a memory address rather than a direct memory access (DMA) operation. But because AEN was asserted low to all cards, each card had to be physically configured to respond to a different range of I/O or memory addresses to avoid conflicts. This address differentiation was usually accomplished when installing the boards by setting microswitches on dual in-line packages (DIP) or by connecting jumpers on each board. Improperly setting these switches could result in conflicts on a read or write to a particular I/O or memory address and could even result in physical hardware damage.
While the ISA standard provided 16 bits of I/O addressing, in developing boards for PC-compatible computers, vendors often only used or decoded the lower 10 bits. Thus, to be fully compatible with the available boards, the I/O address space of the ISA bus effectively was only from 0 to 03 FFh. Thus, a large portion of the I/O space was unusable.
Another corresponding limitation of the ISA bus involved the DMA channels and interrupt lines. The PC offered several DMA channels and interrupt lines for third party expansion boards to utilize, however, because each DMA channel and interrupt line would have to be physically configured, the potential existed for conflicts in this area also. System resources would also reserve several of the DMA channels and interrupt lines for themselves, thus further limiting the number of DMA channels and interrupts line available to third party boards, and further compounding the problem.
The EISA bus standard has resolved this problem to some extent. The EISA bus definition provides for a conflict-free I/O address space for each slot. This is fully described in U.S. Pat. No. 4,999,805 and the EISA Specification, Version 3.1, which is Appendix 1 of U.S. Pat. No. 4,101,492, both of which are hereby incorporated by reference. The expansion board manufacturers include a configuration file with each EISA expansion board, and optionally, with switch programmable ISA products. A configuration utility program provided by the system manufacturer uses the information contained in the configuration files to determine a conflict-free configuration of the system resources. The configuration utility stores the configuration and initialization information into non-volatile memory and saves a backup copy on diskette. Details of this configuration process are provided in Ser. No. 07/293,315, entitled "Method and Apparatus for Configuration of Computer System and Circuit Boards," allowed on May 10, 1993, which is hereby incorporated by reference. The system ROM power up routines use the initialization information to initialize the system during power up, and device drivers use the configuration information to configure the expansion boards during operation.
However, this slot specific addressing does not help with ISA boards. Slot specific ISA board disabling can prevent such physical conflicts between two boards during their initialization. Briefly, a mask register is provided to mask off the AEN signal to selected slots. Details are provided in Ser. No. 08/145,400, entitled "Method of and Apparatus for Disabling Individual Slots on a Computer Bus," filed Oct. 29, 1993, which is hereby incorporated by reference.
Further, the slot specific addressing is of no assistance with memory operations, as the EISA bus standard does not provide for slot specific memory spaces for ISA cards.
Determining what addresses that board responds to is not trivial. Unlike EISA boards, ISA boards do not provide an identification register. Thus, the occupied address space of an ISA board must be determined in some other way.
During the booting or power on self test (POST) operation, the computer determines if any option ROMs are present on the installed circuit boards. If so, an initialization routine in the ROM is executed. It is at this time that the circuit board enables or reserves its selected DMA and interrupt channels by properly programming the DMA and interrupt controllers. Because ISA boards do not include standardized ways to indicate the selected DMA and interrupt channels, they cannot be determined by reading a location on the circuit board. Thus, even the availability of slot specific operations and selective addressing does not reveal what DMA and interrupt resources are used.
It would be desirable to provide the functionality of EISA configuration software for ISA boards. That is, it would be desirable for the system to be able to determine what ISA boards were installed in which slots, and to appropriately respond to any conflicts or mismapping of those devices. Finally, it would be desirable to determine where an ISA board is mapped in the address and memory space and to configure the system accordingly. To do this, it is necessary to obtain all of the information possible from a given ISA board. The related applications detail techniques do determine active address locations, but do not provide DMA or interrupt information, which can further characterize a board and allow conflict free setup. So it would be desirable to be able to determine the DMA and interrupt resources utilized by as given circuit board to be able it to be characterized and matched.